Requirements that increasing levels of functionality be integrated into single substrate integrated circuit (IC) devices may create a pressing need to increase the number of semiconductor devices fabricated into a single substrate. In addition, demands for increasing levels of processing performance may also require that devices operate at faster speeds, as measured in millions of operations per second (MOPS), for example. The two requirements may drive demands that semiconductor fabrication technologies, and design rules enable the design and manufacture of semiconductor devices with increasingly small geometries.
However, as semiconductor device geometries become increasingly smaller, the likelihood of leakage currents in such devices may increase. Leakage currents in semiconductor devices may result in the device continuing to conduct a current under circuit conditions in which the intention was that the device not conduct a current.
One approach to addressing the leakage current limitation may be to insert switching circuitry, which isolates the semiconductor device circuitry from a common voltage source, such as a supply voltage often referred to as VDD. The switching circuitry may utilize a control signal, wherein the common voltage source or a buffered version thereof, may be coupled to the semiconductor device circuitry when the switching circuitry receives an ON control signal. Conversely, the common voltage source may be isolated from the semiconductor device circuitry when the switching circuitry receives an OFF control signal.
The utilization of switching circuitry may introduce a new set of limitations, however. For example, when the switching circuitry receives an ON control signal, the switching circuitry, and/or common voltage source, may deliver a common voltage level to semiconductor circuitry, wherein the semiconductor circuitry may be modeled as a load impedance comprising reactive and/or resistive components. Under these circumstances, the switching circuitry and/or common voltage source may be required to supply a large transient, or in-rush, current when driving the semiconductor circuitry from a voltage, such as ground, to the common voltage, VDD. Following the transient interval, the current supplied by the switching circuitry may settle to a quiescent current level.
Thus, one limitation when utilizing switching circuitry for common voltage isolation is that the switching circuitry, and/or common voltage source, may require buffers that are able to supply comparatively large transient in-rush current levels when the control voltage causes the switching circuitry to couple the semiconductor circuitry to the common voltage. This may mean, however, that the buffers may be over-designed in relation to the quiescent current level requirements. For example, the peak value for the in-rush current level required of the buffers may be 50 mA, whereas the quiescent current level may be 15 mA.
Power sequencing is another approach, which may be utilized to address the limitations associated with large in-rush current levels. In a power sequencing approach, the switching circuitry may include sequence control circuitry that couples a first portion of the semiconductor circuitry to the common voltage source. When the first portion of the semiconductor circuitry has reached the quiescent current level, the sequence control circuitry may enable the switching circuitry to couple a second portion of the semiconductor circuitry to the common voltage source. The sequencing may continue until a final portion of the semiconductor circuitry is coupled to the common voltage source.
Where power sequencing may reduce the peak value for the in-rush current level, it may require additional circuitry, add complexity to the start up sequence for a circuit, and may also result in longer time intervals for turning on semiconductor circuitry. This, in turn, may negatively impact the processing speed and/or performance of the circuitry. In applications, such as wireless communications, the start up time interval when utilizing a power sequencing approach may be too long.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.